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The Assembler generates fixed code allocations, consequently no linking is necessary.
The Assembler runs under Microsoft Windows 3.11, Microsoft Windows95 and Microsoft Windows NT. In addition, there is an MS-DOS command line version.
The instruction set of the AVR family of microcontrollers is only briefly described, refer to the AVR Data Book in order to get more detailed knowledge of the instruction set for the different microcontrollers.
Code lines should be limited to 120 characters.
Every input line can be preceded by a label, which is an alphanumeric string terminated by a colon. Labels are used as targets for jump and branch instructions and as variable names in Program memory and RAM.
An input line may take one of the four following forms:
[label:] directive [operands] [Comment]A comment has the following form:
[label:] instruction [operands] [Comment]
Comment
Empty line
; [Text]Items placed in braces are optional. The text between the comment-delimiter (;) and the end of line (EOL) is ignored by the Assembler. Labels, instructions and directives are described in more detail later.
label: .EQU var1=100 ; Set var1 to 100 (Directive)Note that there are no restrictions with respect to column placement of labels, directives, comments or instructions.
.EQU var2=200 ; Set var2 to 200test: rjmp test ; Infinite loop (Instruction)
; Pure comment line; Another comment line
Mnemonic | Operands | Description | Operation | Flags | Cycles |
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1 |
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1 |
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1 |
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1 |
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1 |
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1 |
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1 |
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1 |
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1 |
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1 |
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1 |
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1 |
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1 |
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1 |
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1 |
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1 |
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1 |
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1 |
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1 |
SER | Rd | Set Register | Rd = $FF | None | 1 |
ADIW | Rdl,K6 | Add Immediate to Word | Rdh:Rdl = Rdh:Rdl + K6 | Z,C,N,V,S | 2 |
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2 |
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2 |
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2 |
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2 |
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2 |
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2 |
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2 |
Mnemonic | Operands | Description | Operation | Flags | Cycles |
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2 |
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2 |
EIJMP | None | Extended Indirect Jump (Z) | STACK = PC+1, PC(15:0) = Z, PC(21:16) = EIND | None | 2 |
JMP | k | Jump | PC = k | None | 3 |
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4* |
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4* |
EICALL | None | Extended Indirect Call to (Z) | STACK = PC+1, PC(15:0) = Z, PC(21:16) =EIND | None | 4* |
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5* |
RET | None | Subroutine Return | PC = STACK | None | 4/5* |
RETI | None | Interrupt Return | PC = STACK | I | 4/5* |
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3 |
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1 |
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1 |
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1 |
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3 |
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3 |
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3 |
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3 |
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2 |
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2 |
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2 |
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2 |
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2 |
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2 |
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2 |
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2 |
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2 |
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2 |
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2 |
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2 |
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2 |
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2 |
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2 |
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2 |
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2 |
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2 |
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2 |
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2 |
Mnemonic | Operands | Description | Operation | Flags | Cycles |
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1 |
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1 |
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1 |
LDS | Rd,k | Load Direct | Rd = (k) | None | 2* |
LD | Rd,X | Load Indirect | Rd = (X) | None | 2* |
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2* |
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2* |
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2* |
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2* |
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2* |
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2* |
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2* |
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2* |
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2* |
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2* |
STS | k,Rr | Store Direct | (k) = Rr | None | 2* |
ST | X,Rr | Store Indirect | (X) = Rr | None | 2* |
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2* |
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2* |
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2* |
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2 |
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2 |
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2 |
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2 |
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2 |
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2 |
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2 |
LPM | None | Load Program Memory | R0 = (Z) | None | 3 |
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3 |
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3 |
ELPM | None | Extended Load Program Memory | R0 = (RAMPZ:Z) | None | 3 |
ELPM | Rd,Z | Extended Load Program Memory | Rd = (RAMPZ:Z) | None | 3 |
ELPM | Rd,Z+ | Extended Load Program Memory and Post Increment | Rd = (RAMPZ:Z), Z = Z+1 | None | 3 |
SPM | None | Store Program Memory | (Z) = R1:R0 | None | - |
ESPM | None | Extended Store Program Memory | (RAMPZ:Z) = R1:R0 | None | - |
IN | Rd,P | In Port | Rd = P | None | 1 |
OUT | P,Rr | Out Port | P = Rr | None | 1 |
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2 |
POP | Rd | Pop register from Stack | Rd = STACK | None | 2 |
Mnemonic | Operands | Description | Operation | Flags | Cycles |
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1 |
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1 |
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1 |
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1 |
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1 |
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1 |
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1 |
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1 |
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2 |
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2 |
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1 |
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1 |
SEC | None | Set carry flag | C =1 | C | 1 |
CLC | None | Clear carry flag | C = 0 | C | 1 |
SEN | None | Set negative flag | N = 1 | N | 1 |
CLN | None | Clear negative flag | N = 0 | N | 1 |
SEZ | None | Set zero flag | Z = 1 | Z | 1 |
CLZ | None | Clear zero flag | Z = 0 | Z | 1 |
SEI | None | Set interrupt flag | I = 1 | I | 1 |
CLI | None | Clear interrupt flag | I = 0 | I | 1 |
SES | None | Set signed flag | S = 1 | S | 1 |
CLN | None | Clear signed flag | S = 0 | S | 1 |
SEV | None | Set overflow flag | V = 1 | V | 1 |
CLV | None | Clear overflow flag | V = 0 | V | 1 |
SET | None | Set T-flag | T = 1 | T | 1 |
CLT | None | Clear T-flag | T = 0 | T | 1 |
SEH | None | Set half carry flag | H = 1 | H | 1 |
CLH | None | Clear half carry flag | H = 0 | H | 1 |
NOP | None | No operation | None | None | 1 |
SLEEP | None | Sleep | See instruction manual | None | 1 |
WDR | None | Watchdog Reset | See instruction manual | None | 1 |
The operands have the following forms:
Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)
Syntax:
LABEL: .BYTE expression
Example:
.DSEG
var1: .BYTE 1
; reserve 1 byte to var1
table: .BYTE tab_size ; reserve
tab_size bytes
.CSEG
ldi r30,low(var1)
; Load Z register low
ldi r31,high(var1)
; Load Z register high
ld r1,Z
; Load VAR1 into register 1
Syntax:
.CSEG
Example:
.DSEG
; Start data segment
vartab: .BYTE 4
; Reserve 4 bytes in SRAM
.CSEG
; Start code segment
const: .DW 2
; Write 0x0002 in prog.mem.
mov r1,r0
; Do something
The expression list is a sequence of expressions, delimited by commas. Each expression must evaluate to a number between -128 and 255. If the expression evaluates to a negative number, the 8 bits twos complement of the number will be placed in the program memory or EEPROM memory location.
If the DB directive is given in a Code Segment and the expressionlist contains more than one expression, the expressions are packed so that two bytes are placed in each program memory word. If the expressionlist contains an odd number of expressions, the last expression will be placed in a program memory word of its own, even if the next line in the assemby code contains a DB directive.
Syntax:
LABEL: .DB expressionlist
Example:
.CSEG
consts: .DB 0, 255, 0b01010101, -128, 0xaa
.ESEG
const2: .DB 1,2,3
Syntax:
.DEF Symbol=Register
Example:
.DEF temp=R16
.DEF ior=R0
.CSEG
ldi temp,0xf0 ; Load 0xf0 into temp register
in ior,0x3f ; Read SREG into ior register
eor temp,ior ; Exclusive or temp and ior
Syntax:
.DEVICE AT90S1200 |AT90S2313 | AT90S2323 | AT90S2333 | AT90S2343
| AT90S4414 | AT90S4433 | AT90S4434 | AT90S8515 | AT90S8534 | AT90S8535
| ATtiny11 | ATtiny12 | ATtiny22 | ATmega603 | ATmega103
Example:
.DEVICE AT90S1200 ; Use the AT90S1200
.CSEG
push r30
; This statement will generate a warning
; since the specified device does not
; have this instruction
Syntax:
.DSEG
Example:
.DSEG
; Start data segment
var1: .BYTE 1
; reserve 1 byte to var1
table: .BYTE tab_size
; reserve tab_size bytes.
.CSEG
ldi r30,low(var1)
; Load Z register low
ldi r31,high(var1)
; Load Z register high
ld r1,Z
; Load var1 into register 1
The expression list is a sequence of expressions, delimited by commas. Each expression must evaluate to a number between -32768 and 65535. If the expression evaluates to a negative number, the 16 bits twos complement of the number will be placed in the program memory or EEPROM memory location.
Syntax:
LABEL: .DW expressionlist
Example:
.CSEG
varlist: .DW 0, 0xffff, 0b1001110001010101, -32768, 65535
.ESEG
eevarlst: .DW 0,0xffff,10
Syntax:
.ENDMACRO
Example:
.MACRO SUBI16
; Start macro definition
subi r16,low(@0)
; Subtract low byte
sbci r17,high(@0)
; Subtract high byte
.ENDMACRO
Syntax:
.EQU label = expression
Example:
.EQU io_offset = 0x23
.EQU porta = io_offset + 2
.CSEG
; Start code segment
clr r2
; Clear register 2
out porta,r2 ;
Write to Port A
Syntax:
.ESEG
Example:
.DSEG
; Start data segment
var1: .BYTE 1
; reserve 1 byte to var1
table: .BYTE tab_size ; reserve tab_size bytes.
.ESEG
eevar1: .DW 0xffff ;
initialize 1 word in EEPROM
Syntax:
.EXIT
Example:
.EXIT ; Exit this file
Syntax:
.INCLUDE "filename"
Example:
; iodefs.asm:
.EQU sreg = 0x3f ; Status register
.EQU sphigh = 0x3e ; Stack pointer high
.EQU splow = 0x3d ; Stack pointer
low
; incdemo.asm
.INCLUDE iodefs.asm ; Include I/O definitions
in r0,sreg
; Read status register
Syntax:
.LIST
Example:
.NOLIST
; Disable listfile generation
.INCLUDE "macro.inc" ; The included files will not
.INCLUDE "const.def" ; be shown in the listfile
.LIST
; Reenable listfile generation
Syntax:
.LISTMAC
Example:
.MACRO MACX ; Define
an example macro
add r0,@0
; Do something
eor r1,@1
; Do something
.ENDMACRO
; End macro definition
.LISTMAC
; Enable macro expansion
MACX r2,r1 ; Call
macro, show expansion
By default, only the call to the Macro is shown on the listfile generated
by the Assembler. In order to include the macro expansion in the listfile,
a LISTMAC directive must be used. A macro is marked with a + in the opcode
field of the listfile.
Syntax:
.MACRO macroname
Example:
.MACRO SUBI16
; Start macro definition
subi @1,low(@0)
; Subtract low byte
sbci @2,high(@0)
; Subtract high byte
.ENDMACRO
; End macro definition
.CSEG
; Start code segment
SUBI16 0x1234,r16,r17
; Sub.0x1234 from r17:r16
Syntax:
.NOLIST
Example:
.NOLIST
; Disable listfile generation
.INCLUDE "macro.inc" ; The included files will
not
.INCLUDE "const.def" ; be shown in the listfile
.LIST
; Reenable listfile generation
Syntax:
.ORG expression
Example:
.DSEG
; Start data segment
.ORG 0x37
; Set SRAM address to hex 37
variable: .BYTE 1 ; Reserve a byte at SRAM adr.37H
.CSEG
.ORG 0x10
; Set Program Counter to hex 10
mov r0,r1
; Do something
Syntax:
.SET label = expression
Example:
.SET io_offset = 0x23
.SET porta = io_offset + 2
.CSEG
; Start code segment
clr r2
; Clear register 2
out porta,r2 ;
Write to Port A
The following operators are defined:
To create a new assembly file click the button on the toolbar or choose File>>New (ALT-F N) from the menu. To open an existing file click the button on the toolbar or choose File>>Open (ALT-F O) from the menu.
To move the insertion point with the keyboard, use the following keys
or key combinations:
To move the insertion point: | Press: |
to the right in a line of text | Right arrow key |
to the left in a line of text | Left arrow key |
up in a body of text | Up arrow key |
down in a body of text | Down arrow key |
to the beginning of a line of text | Home |
to the end of a line of text | End |
to the beginning of the file | Ctrl+Home |
to the end of the file | Ctrl+End |
To: | Press: |
insert a space | Spacebar |
delete a character to the left | Backspace |
delete a character to the right | Del |
end a line | Enter |
indent a line | Tab |
insert a tab stop | Tab |
To join two lines, move the insertion point to the beginning of the line to move, and press Backspace. The editor joins the line with the line above.
Selecting text with the keyboard:
Replacing text:
To move text:
To copy text:
To undo the last edit click the button on the toolbar or choose Edit>>Undo (Alt+Backspace) from the menu.
If the message window line is doubleclicked, the file containing the error becomes the active window, and the cursor is placed at the beginning of the line containing the error. If the file containing the error is not opened (for instance an included file), then the file is automatically opened.
Note that this function points to lines in the assembled file. This means that if lines are added or removed in the source file, the file must be reassembled in order to get the line numbers right.
The Wrap relative jumps option tells the Assembler to use wrapping of addresses. This feature should only be used when assembling for devices with 4K words of program memory. Using this option on such devices, the relative jump and call instructions will reach the entire program memory.
The Save before assemble option makes the Assembler automatically save the contents of the editor before assembling is done.
The Close all windows before exit option will ensure that there are no windows active the next time the assembler is started.